Feed-forward circuit to improve intermodulation distortion performance of radio-frequency switch

ABSTRACT

A radio-frequency (RF) switch includes a field-effect transistor (FET) disposed between a first node and a second node, the FET having a source, a drain, a gate, and a body. The RF switch further includes a coupling circuit including a first path and a second path, the first path being connected between the gate and one of the source or the drain via a first resistor in series with a first capacitor, the second path being connected between the body and the one of the source or the drain via a second resistor in series with a second capacitor, the coupling circuit configured to allow discharge of interface charge from either or both of the gate and body.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/460,675, filed on Mar. 16, 2017, and entitled FEED-FORWARD CIRCUIT TOIMPROVE INTERMODULATION DISTORTION PERFORMANCE OF RADIO-FREQUENCYSWITCH, which is a continuation-in-part of U.S. patent application Ser.No. 14/843,212, filed on Sep. 2, 2015, and entitled RADIO-FREQUENCYSWITCH HAVING DYNAMIC BODY COUPLING, which is a continuation-in-part ofU.S. patent application Ser. No. 13/936,180, filed on Jul. 6, 2013, andentitled CIRCUITS, DEVICES, METHODS AND APPLICATIONS RELATED TOSILICON-ON-INSULATOR BASED RADIO-FREQUENCY SWITCHES, which claims thebenefit of priority under 35 U.S.C. § 119(e) to U.S. ProvisionalApplication No. 61/669,055, filed on Jul. 7, 2012, and entitledCIRCUITS, DEVICES, METHODS AND APPLICATIONS RELATED TOSILICON-ON-INSULATOR BASED RADIO-FREQUENCY SWITCHES, the disclosures ofwhich are all hereby incorporated by reference in their entireties forall purposes.

BACKGROUND Field

The present disclosure generally relates to the field of electronics,and more particularly, to radio-frequency switches.

Description of Related Art

Radio-frequency (RF) switches, such as transistor switches, can be usedto switch signals between one or more poles and one or more throws.Transistor switches, or portions thereof, can be controlled throughtransistor biasing and/or coupling. Design and use of bias and/orcoupling circuits in connection with RF switches can affect switchingperformance.

SUMMARY

Certain embodiments disclosed herein provide a radio-frequency (RF)switch including a plurality of field-effect transistors (FETs)connected in series between first and second nodes, each FET having agate and a body. The RF switch may further include a compensationnetwork including a gate-coupling circuit that couples the gates of eachpair of neighboring FETs, the compensation network further including abody-coupling circuit that couples the bodies of each pair ofneighboring FETs. In certain embodiments, at least some of the FETs aresilicon-on-insulator (SOI) FETs. The gate-coupling circuit may include acapacitor and possibly a resistor in series with the capacitor.

In certain embodiments, the gate-coupling circuit includes a resistor.The body-coupling circuit may include a capacitor. The body-couplingcircuit may further include a resistor in series with the capacitor. Incertain embodiments, the body-coupling circuit includes a resistor.

Certain embodiments disclosed herein provide a process for operating aradio-frequency (RF) switch. The process may include controlling aplurality of field-effect transistors (FETs) connected in series betweenfirst and second nodes so that the FETs are collectively in an ON stateor an OFF state, each FET having a gate and a body. The process mayfurther include coupling the gates of each of neighboring FETs to reducevoltage swings across each of the plurality of FETs, and coupling thebodies of each of neighboring FETs to reduce voltage swings across eachof the plurality of FETs.

Certain embodiments disclosed herein provide a semiconductor dieincluding a semiconductor substrate and a plurality of field-effecttransistors (FETs) formed on the semiconductor substrate and connectedin series, each FET including a gate and a body. The semiconductor diemay further include a compensation network formed on the semiconductorsubstrate, the compensation network including a gate-coupling circuitthat couples the gates of each pair of neighboring FETs, thecompensation network further including a body-coupling circuit thatcouples the bodies of each pair of neighboring FETs.

The semiconductor die may further including an insulator layer disposedbetween the FETs and the semiconductor substrate. In certainembodiments, the die is a silicon-on-insulator (SOI) die.

Certain embodiments provide a process for fabricating a semiconductordie. The process may include providing a semiconductor substrate andforming a plurality of field-effect transistors (FETs) on thesemiconductor substrate so as to be connected in series, each FET havinga gate and a body. The process may further include forming agate-coupling circuit on the semiconductor substrate to couple the gatesof each pair of neighboring FETs, and forming a body-coupling circuit onthe semiconductor substrate to couple the bodies of each pair ofneighboring FETs. In certain embodiments, the process further includesforming an insulator layer between the FETs and the semiconductorsubstrate.

Certain embodiments disclosed herein provide a radio-frequency (RF)switch module including a packaging substrate configured to receive aplurality of components and a semiconductor die mounted on the packagingsubstrate, the die including a plurality of field-effect transistors(FETs) connected in series, each FET including a gate and a gate. The RFswitch module further includes a compensation network including agate-coupling circuit that couples the gates of each pair of neighboringFETs, the compensation network further including a body-coupling circuitthat couples the bodies of each pair of neighboring FETs.

The semiconductor die may be a silicon-on-insulator (SOI) die. Incertain embodiments, the compensation network is part of the samesemiconductor die as the plurality of FETs. The compensation network maybe part of a second die mounted on the packaging substrate. In certainembodiments, the compensation network is disposed at a location outsideof the semiconductor die.

Certain embodiments disclosed herein provide a wireless device includinga transceiver configured to process RF signals and an antenna incommunication with the transceiver configured to facilitate transmissionof an amplified RF signal. The wireless device further includes a poweramplifier connected to the transceiver and configured to generate theamplified RF signal, and a switch connected to the antenna and the poweramplifier and configured to selectively route the amplified RF signal tothe antenna, the switch including a plurality of field-effecttransistors (FETs) connected in series, each FET including a gate and agate, the switch further including a compensation network having agate-coupling circuit that couples the gates of each pair of neighboringFETs and a body-coupling circuit that couples the bodies of each pair ofneighboring FETs.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments are depicted in the accompanying drawings forillustrative purposes, and should in no way be interpreted as limitingthe scope of the inventions. In addition, various features of differentdisclosed embodiments can be combined to form additional embodiments,which are part of this disclosure. Throughout the drawings, referencenumbers may be reused to indicate correspondence between referenceelements.

FIG. 1 schematically shows a radio-frequency (RF) switch configured toswitch one or more signals between one or more poles and one or morethrows.

FIG. 2 shows that the RF switch 100 of FIG. 1 can include an RF core andan energy management (EM) core.

FIG. 3 shows an example of the RF core implemented in ansingle-pole-double-throw (SPDT) configuration.

FIG. 4 shows an example of the RF core implemented in an SPDTconfiguration where each switch arm can include a plurality offield-effect transistors (FETs) connected in series.

FIG. 5 schematically shows that controlling of one or more FETs in an RFswitch can be facilitated by a circuit configured to bias and/or coupleone or more portions of the FETs.

FIG. 6 shows examples of the bias/coupling circuit implemented ondifferent parts of a plurality of FETs in a switch arm.

FIGS. 7A and 7B show plan and side sectional views of an examplefinger-based FET device implemented in a silicon-on-insulator (SOI)configuration.

FIGS. 8A and 8B show plan and side sectional views of an example of amultiple-finger FET device implemented in an SOI configuration.

FIG. 9 shows a first example of an RF switch circuit having a non-linearcapacitor connected to a source terminal of an FET and configured to,for example, cancel or reduce non-linearity effects generated by theFET.

FIG. 10 shows that one or more features of FIG. 9 can be implemented ina switch arm having a plurality of FETs.

FIGS. 11A-11F show variations of a second example of an RF switchcircuit where either or both of gate and body terminals of an FET can becoupled with a source terminal by one or more coupling circuits having acapacitor in series with a resistor to, for example, allow discharge ofinterface charge from the coupled gate and/or body.

FIGS. 12A-12F show that one or more features of FIGS. 11A-11F can beimplemented in switch arms having a plurality of FETs.

FIGS. 13A and 13B show variations of a fifth example of an RF switchcircuit where extra resistance can be provided in a switchable mannerfor either or both of a gate and a body of an FET to, for example,provide improved intermodulation distortion (IMD) performance.

FIGS. 14A and 14B show that one or more features of FIGS. 13A and 13Bcan be implemented in switch arms having a plurality of FETs.

FIG. 15 shows an example of an RF switching configuration including oneor more capacitors to, for example, inhibit a low-frequency blocker frommixing with a fundamental frequency.

FIG. 16 shows an example where the switching configuration of FIG. 15 isin a transmit mode.

FIGS. 17A-17D show examples of how various components for biasing,coupling, and/or facilitating the example configurations of FIGS. 9-16can be implemented.

FIGS. 18A and 18B show an example of a packaged module that can includeone or more features described herein.

FIG. 19 shows that in some embodiments, one or more features of thepresent disclosure can be implemented in a switch device such as asingle-pole-multi-throw (SPMT) switch configured to facilitatemulti-band multi-mode wireless operation.

FIG. 20 shows an example of a wireless device that can include one ormore features described herein.

FIG. 21 shows that in some implementations, one or more featuresassociated with a given example configuration can be combined with oneor more features associated with another example configuration.

DETAILED DESCRIPTION

The headings provided herein, if any, are for convenience only and donot necessarily affect the scope or meaning of the claimed invention.

Example Components of a Switching Device:

FIG. 1 schematically shows a radio-frequency (RF) switch 100 configuredto switch one or more signals between one or more poles 102 and one ormore throws 104. In some embodiments, such a switch can be based on oneor more field-effect transistors (FETs) such as silicon-on-insulator(SOI) FETs. When a particular pole is connected to a particular throw,such a path is commonly referred to as being closed or in an ON state.When a given path between a pole and a throw is not connected, such apath is commonly referred to as being open or in an OFF state.

FIG. 2 shows that in some implementations, the RF switch 100 of FIG. 1can include an RF core 110 and an energy management (EM) core 112. TheRF core 110 can be configured to route RF signals between the first andsecond ports. In the example single-pole-double-throw (SPDT)configuration shown in FIG. 2, such first and second ports can include apole 102 a and a first throw 104 a, or the pole 102 a and a second throw104 b.

In some embodiments, EM core 112 can be configured to supply, forexample, voltage control signals to the RF core. The EM core 112 can befurther configured to provide the RF switch 100 with logic decodingand/or power supply conditioning capabilities.

In some embodiments, the RF core 110 can include one or more poles andone or more throws to enable passage of RF signals between one or moreinputs and one or more outputs of the switch 100. For example, the RFcore 110 can include a single-pole double-throw (SPDT or SP2T)configuration as shown in FIG. 2.

In the example SPDT context, FIG. 3 shows a more detailed exampleconfiguration of an RF core 110. The RF core 110 is shown to include asingle pole 102 a coupled to first and second throw nodes 104 a, 104 bvia first and second transistors (e.g., FETs) 120 a, 120 b. The firstthrow node 104 a is shown to be coupled to an RF ground via an FET 122 ato provide shunting capability for the node 104 a. Similarly, the secondthrow node 104 b is shown to be coupled to the RF ground via an FET 122b to provide shunting capability for the node 104 b.

In an example operation, when the RF core 110 is in a state where an RFsignal is being passed between the pole 102 a and the first throw 104 a,the FET 120 a between the pole 102 a and the first throw node 104 a canbe in an ON state, and the FET 120 b between the pole 102 a and thesecond throw node 104 b can be in an OFF state. For the shunt FETs 122a, 122 b, the shunt FET 122 a can be in an OFF state so that the RFsignal is not shunted to ground as it travels from the pole 102 a to thefirst throw node 104 a. The shunt FET 122 b associated with the secondthrow node 104 b can be in an ON state so that any RF signals or noisearriving at the RF core 110 through the second throw node 104 b isshunted to the ground so as to reduce undesirable interference effectsto the pole-to-first-throw operation.

Although the foregoing example is described in the context of asingle-pole-double-throw configuration, it will be understood that theRF core can be configured with other numbers of poles and throws. Forexample, there may be more than one poles, and the number of throws canbe less than or greater than the example number of two.

In the example of FIG. 3, the transistors between the pole 102 a and thetwo throw nodes 104 a, 104 b are depicted as single transistors. In someimplementations, such switching functionalities between the pole(s) andthe throw(s) can be provided by switch arm segments, where each switcharm segment includes a plurality of transistors such as FETs.

An example RF core configuration 130 of an RF core having such switcharm segments is shown in FIG. 4. In the example, the pole 102 a and thefirst throw node 104 a are shown to be coupled via a first switch armsegment 140 a. Similarly, the pole 102 a and the second throw node 104 bare shown to be coupled via a second switch arm segment 140 b. The firstthrow node 104 a is shown to be capable of being shunted to an RF groundvia a first shunt arm segment 142 a. Similarly, the second throw node104 b is shown to be capable of being shunted to the RF ground via asecond shunt arm segment 142 b.

In an example operation, when the RF core 130 is in a state where an RFsignal is being passed between the pole 102 a and the first throw node104 a, all of the FETs in the first switch arm segment 140 a can be inan ON state, and all of the FETs in the second switch arm segment 104 bcan be in an OFF state. The first shunt arm 142 a for the first thrownode 104 a can have all of its FETs in an OFF state so that the RFsignal is not shunted to ground as it travels from the pole 102 a to thefirst throw node 104 a. All of the FETs in the second shunt arm 142 bassociated with the second throw node 104 b can be in an ON state sothat any RF signals or noise arriving at the RF core 130 through thesecond throw node 104 b is shunted to the ground so as to reduceundesirable interference effects to the pole-to-first-throw operation.

Again, although described in the context of an SP2T configuration, itwill be understood that RF cores having other numbers of poles andthrows can also be implemented.

In some implementations, a switch arm segment (e.g., 140 a, 140 b, 142a, 142 b) can include one or more semiconductor transistors such asFETs. In some embodiments, an FET may be capable of being in a firststate or a second state and can include a gate, a drain, a source, and abody (sometimes also referred to as a substrate. In some embodiments, anFET can include a metal-oxide-semiconductor field effect transistor(MOSFET). In some embodiments, one or more FETs can be connected inseries forming a first end and a second end such that an RF signal canbe routed between the first end and the second end when the FETs are ina first state (e.g., ON state).

At least some of the present disclosure relates to how an FET or a groupof FETs can be controlled to provide switching functionalities indesirable manners. FIG. 5 schematically shows that in someimplementations, such controlling of an FET 120 can be facilitated by acircuit 150 configured to bias and/or couple one or more portions of theFET 120. In some embodiments, such a circuit 150 can include one or morecircuits configured to bias and/or couple a gate of the FET 120, biasand/or couple a body of the FET 120, and/or couple a source/drain of theFET 120.

Schematic examples of how such biasing and/or coupling of differentparts of one or more FETs are described in reference to FIG. 6. In FIG.6, a switch arm segment 140 (that can be, for example, one of theexample switch arm segments 140 a, 140 b, 142 a, 142 b of the example ofFIG. 4) between nodes 144, 146 is shown to include a plurality of FETs120. Operations of such FETs can be controlled and/or facilitated by agate bias/coupling circuit 150 a, and a body bias/coupling circuit 150c, and/or a source/drain coupling circuit 150 b.

Gate Bias/Coupling Circuit

In the example shown in FIG. 6, the gate of each of the FETs 120 can beconnected to the gate bias/coupling circuit 150 a to receive a gate biassignal and/or couple the gate to another part of the FET 120 or theswitch arm 140. In some implementations, designs or features of the gatebias/coupling circuit 150 a can improve performance of the switch arm140. Such improvements in performance can include, but are not limitedto, device insertion loss, isolation performance, power handlingcapability and/or switching device linearity.

Body Bias/Coupling Circuit

As shown in FIG. 6, the body of each FET 120 can be connected to thebody bias/coupling circuit 150 c to receive a body bias signal and/orcouple the body to another part of the FET 120 or the switch arm 140. Insome implementations, designs or features of the body bias/couplingcircuit 150 c can improve performance of the switch arm 140. Suchimprovements in performance can include, but are not limited to, deviceinsertion loss, isolation performance, power handling capability and/orswitching device linearity.

Source/Drain Coupling Circuit

As shown in FIG. 6, the source/drain of each FET 120 can be connected tothe coupling circuit 150 b to couple the source/drain to another part ofthe FET 120 or the switch arm 140. In some implementations, designs orfeatures of the coupling circuit 150 b can improve performance of theswitch arm 140. Such improvements in performance can include, but arenot limited to, device insertion loss, isolation performance, powerhandling capability and/or switching device linearity.

Examples of Switching Performance Parameters:

Insertion Loss

A switching device performance parameter can include a measure ofinsertion loss. A switching device insertion loss can be a measure ofthe attenuation of an RF signal that is routed through the RF switchingdevice. For example, the magnitude of an RF signal at an output port ofa switching device can be less than the magnitude of the RF signal at aninput port of the switching device. In some embodiments, a switchingdevice can include device components that introduce parasiticcapacitance, inductance, resistance, or conductance into the device,contributing to increased switching device insertion loss. In someembodiments, a switching device insertion loss can be measured as aratio of the power or voltage of an RF signal at an input port to thepower or voltage of the RF signal at an output port of the switchingdevice. Decreased switching device insertion loss can be desirable toenable improved RF signal transmission.

Isolation

A switching device performance parameter can also include a measure ofisolation. Switching device isolation can be a measure of the RFisolation between an input port and an output port an RF switchingdevice. In some embodiments, it can be a measure of the RF isolation ofa switching device while the switching device is in a state where aninput port and an output port are electrically isolated, for examplewhile the switching device is in an OFF state. Increased switchingdevice isolation can improve RF signal integrity. In certainembodiments, an increase in isolation can improve wireless communicationdevice performance.

Intermodulation Distortion

A switching device performance parameter can further include a measureof intermodulation distortion (IMD) performance. Intermodulationdistortion (IMD) can be a measure of non-linearity in an RF switchingdevice.

IMD can result from two or more signals mixing together and yieldingfrequencies that are not harmonic frequencies. For example, suppose thattwo signals have fundamental frequencies f₁ and f₂ (f₂>f₁) that arerelatively close to each other in frequency space. Mixing of suchsignals can result in peaks in frequency spectrum at frequenciescorresponding to different products of fundamental and harmonicfrequencies of the two signals. For example, a second-orderintermodulation distortion (also referred to as IMD2) is typicallyconsidered to include frequencies f₁+f₂ f₂−f₁, 2f₁, and 2f₂. Athird-order IMD (also referred to as IMD3) is typically considered toinclude 2f₁+f₂, 2f₁+f₂, f₁+2f₂, f₁−2f₂. Higher order products can beformed in similar manners.

In general, as the IMD order number increases, power levels decrease.Accordingly, second and third orders can be undesirable effects that areof particular interest. Higher orders such as fourth and fifth orderscan also be of interest in some situations.

In some RF applications, it can be desirable to reduce susceptibility tointerference within an RF system. Non linearity in RF systems can resultin introduction of spurious signals into the system. Spurious signals inthe RF system can result in interference within the system and degradethe information transmitted by RF signals. An RF system having increasednon-linearity can demonstrate increased susceptibility to interference.Non-linearity in system components, for example switching devices, cancontribute to the introduction of spurious signals into the RF system,thereby contributing to degradation of overall RF system linearity andIMD performance.

In some embodiments, RF switching devices can be implemented as part ofan RF system including a wireless communication system. IMD performanceof the system can be improved by increasing linearity of systemcomponents, such as linearity of an RF switching device. In someembodiments, a wireless communication system can operate in a multi-bandand/or multi-mode environment. Improvement in intermodulation distortion(IMD) performance can be desirable in wireless communication systemsoperating in a multi-band and/or multi-mode environment. In someembodiments, improvement of a switching device IMD performance canimprove the IMD performance of a wireless communication system operatingin a multi-mode and/or multi-band environment.

Improved switching device IMD performance can be desirable for wirelesscommunication devices operating in various wireless communicationstandards, for example for wireless communication devices operating inthe LTE communication standard. In some RF applications, it can bedesirable to improve linearity of switching devices operating inwireless communication devices that enable simultaneous transmission ofdata and voice communication. For example, improved IMD performance inswitching devices can be desirable for wireless communication devicesoperating in the LTE communication standard and performing simultaneoustransmission of voice and data communication (e.g., SVLTE).

High Power Handling Capability

In some RF applications, it can be desirable for RF switching devices tooperate under high power while reducing degradation of other deviceperformance parameters. In some embodiments, it can be desirable for RFswitching devices to operate under high power with improvedintermodulation distortion, insertion loss, and/or isolationperformance.

In some embodiments, an increased number of transistors can beimplemented in a switch arm segment of a switching device to enableimproved power handling capability of the switching device. For example,a switch arm segment can include an increased number of FETs connectedin series, an increased FET stack height, to enable improved deviceperformance under high power. However, in some embodiments, increasedFET stack height can degrade the switching device insertion lossperformance.

Examples of FET Structures and Fabrication Process Technologies:

A switching device can be implemented on-die, off-die, or somecombination thereon. A switching device can also be fabricated usingvarious technologies. In some embodiments, RF switching devices can befabricated with silicon or silicon-on-insulator (SOI) technology.

As described herein, an RF switching device can be implemented usingsilicon-on-insulator (SOI) technology. In some embodiments, SOItechnology can include a semiconductor substrate having an embeddedlayer of electrically insulating material, such as a buried oxide layerbeneath a silicon device layer. For example, an SOI substrate caninclude an oxide layer embedded below a silicon layer. Other insulatingmaterials known in the art can also be used.

Implementation of RF applications, such as an RF switching device, usingSOI technology can improve switching device performance. In someembodiments, SOI technology can enable reduced power consumption.Reduced power consumption can be desirable in RF applications, includingthose associated with wireless communication devices. SOI technology canenable reduced power consumption of device circuitry due to decreasedparasitic capacitance of transistors and interconnect metallization to asilicon substrate. Presence of a buried oxide layer can also reducejunction capacitance or use of high resistivity substrate, enablingreduced substrate related RF losses. Electrically isolated SOItransistors can facilitate stacking, contributing to decreased chipsize.

In some SOI FET configurations, each transistor can be configured as afinger-based device where the source and drain are rectangular shaped(in a plan view) and a gate structure extends between the source anddrain like a rectangular shaped finger. FIGS. 7A and 7B show plan andside sectional views of an example finger-based FET device implementedon SOI. As shown, FET devices described herein can include a p-type FETor an n-type FET. Thus, although some FET devices are described hereinas p-type devices, it will be understood that various conceptsassociated with such p-type devices can also apply to n-type devices.

As shown in FIGS. 7A and 7B, a pMOSFET can include an insulator layerformed on a semiconductor substrate. The insulator layer can be formedfrom materials such as silicon dioxide or sapphire. An n-well is shownto be formed in the insulator such that the exposed surface generallydefines a rectangular region. Source (S) and drain (D) are shown to bep-doped regions whose exposed surfaces generally define rectangles. Asshown, S/D regions can be configured so that source and drainfunctionalities are reversed.

FIGS. 7A and 7B further show that a gate (G) can be formed on the n-wellso as to be positioned between the source and the drain. The examplegate is depicted as having a rectangular shape that extends along withthe source and the drain. Also shown is an n-type body contact.Formations of the rectangular shaped well, source and drain regions, andthe body contact can be achieved by a number of known techniques. Insome embodiments, the source and drain regions can be formed adjacent tothe ends of their respective upper insulator layers, and the junctionsbetween the body and the source/drain regions on the opposing sides ofthe body can extend substantially all the way down to the top of theburied insulator layer. Such a configuration can provide, for example,reduced source/drain junction capacitance. To form a body contact forsuch a configuration, an additional gate region can be provided on theside so as to allow, for example, an isolated P+ region to contact thePwell.

FIGS. 8A and 8B show plan and side sectional views of an example of amultiple-finger FET device implemented on SOI. Formations of rectangularshaped n-well, rectangular shaped p-doped regions, rectangular shapedgates, and n-type body contact can be achieved in manners similar tothose described in reference to FIGS. 7A and 7B.

The example multiple-finger FET device of FIGS. 8A and 8B can be made tooperate such that a drain of one FET acts as a source of its neighboringFET. Thus, the multiple-finger FET device as a whole can provide avoltage-dividing functionality. For example, an RF signal can beprovided at one of the outermost p-doped regions (e.g., the leftmostp-doped region); and as the signal passes through the series of FETs,the signal's voltage can be divided among the FETs. In such an example,the rightmost p-doped region can act as an overall drain of themulti-finger FET device.

In some implementations, a plurality of the foregoing multi-finger FETdevices can be connected in series as a switch to, for example, furtherfacilitate the voltage-dividing functionality. A number of suchmulti-finger FET devices can be selected based on, for example, powerhandling requirement of the switch.

Examples of Bias and/or Coupling Configurations for ImprovedPerformance:

Described herein are various examples of how FET-based switch circuitscan be biased and/or coupled to yield one or more performanceimprovements. In some embodiments, such biasing/coupling configurationscan be implemented in SOI FET-based switch circuits. It will beunderstood that some of the example biasing/coupling configurations canbe combined to yield a combination of desirable features that may not beavailable to the individual configurations. It will also be understoodthat, although described in the context of RF switching applications,one or more features described herein can also be applied to othercircuits and devices that utilize FETs such as SOI FETs.

DESCRIPTION OF EXAMPLE 1

In some radio-frequency (RF) applications, it is desirable to utilizeswitches having high linearity, as well as management of intermodulationdistortion (IMD) such as IMD3 and IMD2. Such switch-related performancefeatures can contribute significantly to system-level performance ofcellular devices. In the context of silicon-on-oxide (SOI) switches,factors such as substrate-coupling (sometimes also referred to assubstrate parasitics) and SOI-process can limit the performanceachievable.

Such a limitation in performance of SOI switches can be addressed byextensive substrate crosstalk reduction techniques such as capacitiveguard rings, and/or trap rich or deep trench isolation techniques. Suchtechniques typically have associated with them undesirable features suchas being expensive, requiring relatively large areas, and requiringadditional process steps. Also, such technique can yield a desirableeffect that is limited to an isolation feature.

In some implementations, performance of SOI switches can be improved byovercoming or reducing the foregoing effects associated with substrateparasitics and/or process variables. By way of an example, FIG. 9 showsa switch circuit 200 having an SOI FET 120 configured to provideswitching functionality between first and second nodes 144, 146. A gateterminal of the FET 120 is shown to be biased by a bias voltage Vgprovided by a gate bias circuit, and a body terminal of the FET 120 isshown to be biased by a bias voltage Vsb1 provided by a body biascircuit. In some embodiments, the body terminal can be connected to asource terminal, so that both terminals are provided with the biasvoltage Vsb1.

In some embodiments, the source terminal of the FET 120 can be connectedto a non-linear capacitor 202. In embodiments where the FET 120 is aMOSFET device, the capacitor 202 can be a MOSFET capacitor configured toprovide one or more desired capacitance values. The MOS capacitor 202can be configured to generate one or more harmonics to cancel or reducenon-linearity effects generated by the MOSFET 120. The MOS cap 202 isshown to be biased by Vsb2. In some embodiments, either or both of Vsb1and Vsb2 can be adjusted to yield a desired level of non-linearitycancelation. Although described in the context of the source side of theFET 120, it will be understood that the MOS cap 202 can also beimplemented on the drain side of the FET.

FIG. 10 shows a switch arm 210 having a plurality of the switch circuits200 described in reference to FIG. 9. In the example, N such switchcircuits are shown to be connected in series in a stack to provideswitching functionality between terminals 144, 146. In some embodiments,the number (N) of FETs in such a stack can be selected based on powerbeing transferred between the terminals 144, 146. For example, N can belarger for situations involving higher power.

In some embodiments, gate bias voltages (Vg) for the plurality of FETs120 can be substantially the same, and be provided by a common gate biascircuit. Such a common gate bias voltage Vg is shown to be provided tothe gates via a gate resistor Rg. Similarly, body bias voltages (Vsb1)for the plurality of FETs 120 can be substantially the same, and beprovided by a common body bias circuit. Similarly, body bias voltages(Vsb2) for the plurality of MOS capacitors 202 can be substantially thesame, and be provided by a common body bias circuit (not shown). In someimplementations, some or all of the bodies of the FETs 120 and/or theMOS capacitors 202 can be biased separately. Such a configuration can bebeneficial in some situations, depending on the frequency of operation.

In some implementations, the foregoing example configurations describedin reference to FIGS. 9 and 10 can allow significant or substantiallycomplete cancelation of non-linearity effects associated with one ormore SOI FET based RF switches. In some embodiments, such configurationscan be implemented so that minimal or relatively little additional areais required.

Summary of Example 1

According to some implementations, Example 1 relates to aradio-frequency (RF) switch that includes at least one field-effecttransistor (FET) disposed between first and second nodes, with each ofthe at least one FET having a respective source and drain. The switchfurther includes a compensation circuit connected to the respectivesource or the respective drain of each of the at least one FET. Thecompensation circuit is configured to compensate a non-linearity effectgenerated by the at least one FET.

In some embodiments, the FET can be a silicon-on-insulator (SOI) FET. Insome embodiments, the compensation circuit can include a non-linearcapacitor. The non-linear capacitor can include ametal-oxide-semiconductor (MOS) capacitor. The MOS capacitor can beconfigured to generate one or more harmonics to substantially cancel thenon-linearity effect generated by the FET. The MOS capacitor can includean FET structure. The one or more harmonics generated by the MOScapacitor can be controlled at least in part by a body bias signalprovided to the FET structure of the MOS capacitor.

In some embodiments, the non-linear capacitor can be connected to thesource of the FET.

In some embodiments, the switch can further include a gate bias circuitconnected to and configured to provide a bias signal to a gate of theFET.

In some embodiments, the switch can further include a body bias circuitconnected to and configured to provide a bias signal to a body of theFET.

In some embodiments, the first node can be configured to receive an RFsignal having a power value and the second node is configured to outputthe RF signal when the FET is in an ON state. The at least one FET caninclude N FETs connected in series, with the quantity N being selectedto allow the switch circuit to handle the power of the RF signal.

In some implementations, Example 1 relates to a method for operating aradio-frequency (RF) switch. The method includes controlling at leastone field-effect transistor (FET) disposed between first and secondnodes so that each of the at least one FET is in an ON state or an OFFstate. The method further includes compensating a non-linear effect ofthe at least one FET by applying another non-linear signal to arespective source or a respective drain of each of the at least one FET.

In accordance with a number of implementations, Example 1 relates to asemiconductor die that includes a semiconductor substrate and at leastone field-effect transistor (FET) formed on the semiconductor substrate.The die further includes a compensation circuit connected to arespective source or a respective drain of each of the at least one FET.The compensation circuit is configured to compensate a non-linearityeffect generated by the at least one FET.

In some embodiments, the die can further include an insulator layerdisposed between the FET and the semiconductor substrate. The die can bea silicon-on-insulator (SOI) die.

In a number of implementations, Example 1 relates to a method forfabricating a semiconductor die. The method includes providing asemiconductor substrate, and forming at least one field-effecttransistor (FET) on the semiconductor substrate, with each of the atleast one FET having a respective source and a respective drain. Themethod further includes forming a compensation circuit on thesemiconductor substrate. The method further includes connecting thecompensation circuit to the respective source or the respective drain ofeach of the at least one FET to thereby allow the compensation circuitto compensate a non-linearity effect generated by the at least one FET.

In some embodiments, the method can further include forming an insulatorlayer between the FET and the semiconductor substrate.

According to some implementations, Example 1 relates to aradio-frequency (RF) switch module that includes a packaging substrateconfigured to receive a plurality of components. The module furtherincludes a semiconductor die mounted on the packaging substrate, withthe die having at least one field-effect transistor (FET). The modulefurther includes a compensation circuit connected to a respective sourceor a respective drain of each of the at least one FET. The compensationcircuit is configured to compensate a non-linearity effect generated bythe at least one FET.

In some embodiments, the semiconductor die can be a silicon-on-insulator(SOI) die. In some embodiments, compensation circuit can be part of thesame semiconductor die as the at least one FET. In some embodiments, thecompensation circuit can be part of a second die mounted on thepackaging substrate. In some embodiments, the compensation circuit canbe disposed at a location outside of the semiconductor die.

In some implementations, Example 1 relates to a wireless device thatincludes a transceiver configured to process RF signals. The wirelessdevice further includes an antenna in communication with the transceiverconfigured to facilitate transmission of an amplified RF signal. Thewireless device further includes a power amplifier connected to thetransceiver and configured to generate the amplified RF signal. Thewireless device further includes a switch connected to the antenna andthe power amplifier and configured to selectively route the amplified RFsignal to the antenna. The switch includes at least one field-effecttransistor (FET). The switch further includes a compensation circuitconnected to a respective source or a respective drain of each of the atleast one FET. The compensation circuit is configured to compensate anon-linearity effect generated by the at least one FET.

DESCRIPTION OF EXAMPLE 2

As described herein, intermodulation distortion (IMD) can be a measureof unwanted signal added to a desired signal due to mixing products fromother radio-frequency (RF) signals. Such distortions can be particularlydominant in a multi-mode, multi-band environment.

IMD can result from two or more signals mixing together and yieldingfrequencies that are not harmonic frequencies. In some implementations,susceptibility to such interference can be reduced by improvinglinearity of a system, since the system's linearity can govern how muchIMD (and in turn interferences) will occur. Through improved linearityof the system's building blocks (such as an RF switch), an overallsusceptibility of the system to interference can be decreased.

The desire for lower IMD in RF switches can play an important role invarious wireless system designs. There has been a significant amount ofeffort in the wireless industry to reduce IMDs in switches. For exampleLong Term Evolution (LTE) systems can benefit significantly from RFswitches having reduced IMDs. As a more specific example, system designsfor simultaneous voice and data on LTE (SVLTE) can benefit significantlyfrom RF switches having ultra-low levels of IMDs.

In some implementations, a gate terminal and either of source and drainterminals of an FET can be coupled by a circuit for IMD performanceimprovement. For the purpose of description, it will be assumed thatsuch a circuit couples the gate and source terminals; however, it willbe understood that the circuit can couple the gate terminal and thedrain terminal.

In some implementations, a body terminal and either of source and drainterminals of an FET can be coupled by a circuit for IMD performanceimprovement. For the purpose of description, it will be assumed thatsuch a circuit couples the body and source terminals; however, it willbe understood that the circuit can couple the body terminal and thedrain terminal.

In some implementations, each of gate and body terminal and either ofsource and drain terminals of an FET can be coupled by circuits for IMDperformance improvement. For the purpose of description, it will beassumed that such circuits couple each of the gate and body terminals tothe source terminal; however, it will be understood that such couplingscan be made to the drain terminal.

FIGS. 11A-11F show switch circuit examples 220 having an SOI FET 120configured to provide switching functionality between first and secondnodes 144, 146. A gate terminal of the FET 120 is shown to be biasedthrough a gate resistor Rg. The gate resistor Rg can be configured tofloat the gate. FIGS. 11A, 11C and 11E show configurations with aresistive-body connection (with a body resistor Rb, which can beconfigured to float the body); and FIGS. 11B, 11D and 11F showconfigurations with a diode-body connection (with a diode 226).

In each of the examples shown in FIGS. 11A-11F, either or both of gateand body terminals can be coupled with a source terminal by one or morecoupling circuits having a capacitor 222 in series with a resistor 224.For the purpose of description of FIGS. 11A-11F, the coupling circuit isreferred to as an RC circuit.

Such a coupling can allow discharge of interface charge from the coupledgate and/or body. Such discharge of interface charge can lead toimprovement in IMD performance, especially for low-frequency blocker.For configurations where the RC circuit is coupled to the gate, highimpedance can be presented to the low-frequency signal by the RCcircuit, which prevents it from leaking in to the gate, or reduces itsleakage into the gate. Similarly, for configurations where the RCcircuit is coupled to the body, high impedance can be presented to thelow-frequency signal by the RC circuit, which prevents it from leakingin to the body, or reduces its leakage into the body.

FIG. 11A shows a switch circuit 220 where an RC circuit having acapacitor 222 (capacitance C) in series with a resistor 224 (resistanceR) couples a source terminal with a gate terminal of an SOI FET 120. Inthis example, both of the gate and body are floated by their respectiveresistors Rg and Rb.

FIG. 11B shows a switch circuit 220 where an RC circuit having acapacitor 222 (capacitance C) in series with a resistor 224 (resistanceR) couples a source terminal with a gate terminal of an SOI FET 120. Inthis example, the gate is floated by a resistor Rg, and a diode-bodyconnection is provided.

FIG. 11C shows a switch circuit 220 where an RC circuit having acapacitor 222 (capacitance C) in series with a resistor 224 (resistanceR) couples a source terminal with a body terminal of an SOI FET 120. Inthis example, both of the gate and body are floated by their respectiveresistors Rg and Rb.

FIG. 11D shows a switch circuit 220 where an RC circuit having acapacitor 222 (capacitance C) in series with a resistor 224 (resistanceR) couples a source terminal with a body terminal of an SOI FET 120. Inthis example, the gate is floated by a resistor Rg, and a diode-bodyconnection is provided.

FIG. 11E shows a switch circuit 220 where an RC circuit having acapacitor 222 (capacitance C) in series with a resistor 224 (resistanceR) couples a source terminal with a body terminal of an SOI FET 120.Another RC circuit having a capacitor 222′ (capacitance C′) in serieswith a resistor 224′ (resistance R′) couples a source terminal with agate terminal of the FET 120. In this example, both of the gate and bodyare floated by their respective resistors Rg and Rb.

FIG. 11F shows a switch circuit 220 where an RC circuit having acapacitor 222 (capacitance C) in series with a resistor 224 (resistanceR) couples a source terminal with a body terminal of an SOI FET 120.Another RC circuit having a capacitor 222′ (capacitance C′) in serieswith a resistor 224′ (resistance R′) couples a source terminal with agate terminal of the FET 120. In this example, the gate is floated by aresistor Rg, and a diode-body connection is provided.

FIGS. 12A-12F show switch arms 230 having the switch circuits 220described in reference to FIGS. 11A-11F. In each of the examples, N suchswitch circuits are shown to be connected in series to provide switchingfunctionality between terminals 144, 146.

In some embodiments, gate bias voltages (Vg) for the plurality of FETs120 can be substantially the same, and be provided by a common gate biascircuit. Such a common gate bias voltage Vg is shown to be provided tothe gates via a gate resistor Rg. Similarly, body bias voltages (Vb) forthe plurality of FETs 120 can be substantially the same, and be providedby a common body bias circuit for the examples having resistive-bodyconnection.

In some embodiments, some or all of the gates of the FETs 120 can bebiased separately. In some situations, such as when substantially equalvoltage division across the FETs is desired, it can be advantageous toimplement such separate biasing of gates. Similarly, in someembodiments, some or all of the bodies of the FETs 120 can be biasedseparately. In some situations, such as when substantially equal voltagedivision across the FETs is desired, it can be advantageous to implementsuch separate biasing of bodies.

In some implementations, and as described herein, the foregoing exampleconfigurations described in reference to FIGS. 11 and 12 can yieldimprovements in IMD performance, especially for low-frequency blocker.

Summary of Example 2

In a number of implementations, Example 2 relates to a radio-frequency(RF) switch that includes at least one field-effect transistor (FET)disposed between first and second nodes, with each of the at least oneFET having a respective source, drain, gate, and body. The RF switchfurther includes a coupling circuit having at least one of first andsecond paths, with the first path being between the respective source orthe drain and the corresponding gate of each FET, and the second pathbeing between the respective source or the drain and the correspondingbody of each FET. The coupling circuit is configured to allow dischargeof interface charge from either or both of the coupled gate and body.

In some embodiments, the FET can be a silicon-on-insulator (SOI) FET. Insome embodiments, the coupling circuit can include the first path butnot the second path, with the coupling circuit including an RC circuithaving a capacitor in series with a resistor to thereby allow thedischarge from the gate. In some embodiments, the coupling circuit caninclude the second path but not the first path, with the couplingcircuit including an RC circuit having a capacitor in series with aresistor to thereby allow the discharge from the body. In someembodiments, the coupling circuit can include both of the first andsecond paths, with the coupling circuit including first and second RCcircuits. The first RC circuit can have a first capacitor in series witha first resistor to thereby allow the discharge from the gate. Thesecond RC circuit can have a second capacitor in series with a secondresistor to thereby allow the discharge from the body.

In some embodiments, each of the first and second paths can be connectedto the drain. In some embodiments, the RF switch can further include agate resistor connected to the gate and configured to float the gate. Insome embodiments, the RF switch can further include a body resistorconnected to the body and configured to float the body. In someembodiments, the RF switch can further include a diode-body connectionbetween the body and the gate.

In some embodiments, the first node can ge configured to receive an RFsignal having a power value and the second node can be configured tooutput the RF signal when the FET is in an ON state. The at least oneFET can include N FETs connected in series, with the quantity N beingselected to allow the switch circuit to handle the power of the RFsignal.

According to some implementations, Example 2 relates to a method foroperating a radio-frequency (RF) switch. The method includes controllingat least one field-effect transistor (FET) disposed between first andsecond nodes. The method further includes discharging interface chargefrom at least one of a gate and a body of each FET by providing at leastone of first and second paths, with the first path being between asource or a drain and the gate of each FET, and the second path beingbetween the source or the drain and the body of each FET.

In accordance with a number of implementations, Example 2 relates to asemiconductor die that includes a semiconductor substrate and at leastone field-effect transistor (FET) formed on the semiconductor substrate.The die further includes a coupling circuit having at least one of firstand second paths, with the first path being between a source or a drainand a gate of each FET, and the second path being between the source orthe drain and a body of each FET. The coupling circuit is configured toallow discharge of interface charge from either or both of the coupledgate and body.

In some embodiments, the coupling circuit can include at least one RCcircuit having a capacitor in series with a resistor. In someembodiments, the die can further include an insulator layer disposedbetween the FET and the semiconductor substrate. The die can be asilicon-on-insulator (SOI) die.

In some implementations, Example 2 relates to a method for fabricating asemiconductor die. The method includes providing a semiconductorsubstrate and forming at least one field-effect transistor (FET) on thesemiconductor substrate, with each of the at least one FETs having arespective gate, body, source, and drain. The method further includesforming a coupling circuit on the semiconductor substrate. The methodfurther includes forming at least one of first and second paths with thecoupling circuit, with the first path being between the respectivesource or the drain and the respective gate of each FET, and the secondpath being between the respective source or the drain and the respectivebody of each FET. The coupling circuit is configured to allow dischargeof interface charge from either or both of the coupled gate and body.

In some embodiments, the method can further include forming an insulatorlayer between the FET and the semiconductor substrate.

According to a number of implementations, Example 2 relates to aradio-frequency (RF) switch module that includes a packaging substrateconfigured to receive a plurality of components. The module furtherincludes a semiconductor die mounted on the packaging substrate, withthe die having at least one field-effect transistor (FET). The modulefurther includes a coupling circuit having at least one of first andsecond paths, with the first path being between a source or a drain anda gate of each FET, and the second path being between the source or thedrain and a body of each FET. The coupling circuit is configured toallow discharge of interface charge from either or both of the coupledgate and body.

In some embodiments, the semiconductor die can be a silicon-on-insulator(SOI) die. In some embodiments, the coupling circuit can include atleast one RC circuit having a capacitor in series with a resistor. Insome embodiments, the RC circuit can be part of the same semiconductordie as the at least one FET. In some embodiments, at least some of theRC circuit can be part of a second die mounted on the packagingsubstrate. In some embodiments, at least some of the RC circuit can bedisposed at a location outside of the semiconductor die.

In a number of implementations, Example 2 relates to a wireless devicethat includes a transceiver configured to process RF signals. Thewireless device further includes an antenna in communication with thetransceiver configured to facilitate transmission of an amplified RFsignal. The wireless device further includes a power amplifier connectedto the transceiver and configured to generate the amplified RF signal.The wireless device further includes a switch connected to the antennaand the power amplifier and configured to route the amplified RF signalto the antenna. The switch includes at least one field-effect transistor(FET). The switch further includes a coupling circuit having at leastone of first and second paths, with the first path being between asource or a drain and a gate of each FET, and the second path beingbetween the source or the drain and a body of each FET. The couplingcircuit is configured to allow discharge of interface charge from eitheror both of the coupled gate and body.

In some embodiments, the coupling circuit can include at least one RCcircuit having a capacitor in series with a resistor. In someembodiments, the wireless device can be configured to operate in an LTEcommunication system.

DESCRIPTION OF EXAMPLE 3

Intermodulation distortion (IMD) measures an unwanted signal added to adesired signal due to mixing products from other RF signals. Such aneffect can be particularly dominant in a multi-mode, multi-bandenvironment.

IMD can the result from two or more signals mixing together to yieldfrequencies that are not harmonic frequencies.

System designers typically strive to reduce interference susceptibilitythrough, for example, improved linearity. A given system's linearity cangovern how much IMD will occur within it, which in turn can createinterferences. Through improved linearity of the system building blocks,such as an RF switch, the overall susceptibility of a system tointerference can be decreased.

Performance features such as a lower IMD in RF switches can be animportant factor in wireless-device designs. For example, Long TermEvolution (LTE) systems can benefit significantly from RF switcheshaving reduced IMDs. As a more specific example, system designs forsimultaneous voice and data on LTE (SVLTE) can benefit significantlyfrom RF switches having ultra-low levels of IMDs.

FIG. 13A shows a switch circuit example 340 having an SOI FET 120configured to provide switching functionality between first and secondnodes 144, 146. A gate of the FET 120 can be provided with a gate biassignal through a gate resistor (resistance Rg). A body of the FET 120can be provided with a body bias signal through a body resistor(resistance Rb).

In some implementations, extra gate and/or body resistance(s) can beprovided for the FET 120. In the example configuration 340, an extragate resistor (resistance R1) is shown to be connected in series withthe gate resistor Rg. In some embodiments, such an extra gate resistancecan be introduced in a selected manner by, for example, a switch 51(e.g., another FET). For example, opening of the switch 51 results inthe extra resistor R1 being in series with Rg; and closing of 51 resultsin the extra resistor R1 being bypassed when the extra resistance is notrequired or desired (e.g., for improved switching time).

In the example configuration 340, an extra body resistor (resistance R2)is shown to be connected in series with the body resistor Rb. In someembodiments, such an extra body resistance can be introduced in aselected manner by, for example, a switch S2 (e.g., another FET). Forexample, opening of the switch S2 results in the extra resistor R2 beingin series with Rb; and closing of S2 results in the extra resistor R2being bypassed when the extra resistance is not required or desired(e.g., for improved switching time).

In some implementations, the extra resistances for the gate and the bodycan be turned ON or OFF together, or independently from each other. Insome embodiments, only one of the extra resistances can be provided tothe gate or the body. For example, FIG. 13B shows an exampleconfiguration 340 where an extra gate resistance is provided asdescribed in reference to FIG. 13A, but the body is configured with adiode (D) body contact.

FIGS. 14A and 14B show switch arms 350 having the switch circuitsdescribed in reference to FIGS. 13A and 13B. In the exampleconfiguration 350 of FIG. 14A, N switch circuits having gate resistanceRg and body resistance Rb are connected in series to provide switchingfunctionality between terminals 144, 146. A common extra resistance R1is shown to be provided to the gates of the FETs 120; and such an extraresistance R1 can be switched ON and OFF by a common switch S1. A commonextra resistance R2 is shown to be provided to the bodies of the FETs120; and such an extra resistance R2 can be switched ON and OFF by acommon switch S2. In some embodiments, such a switchable extraresistance can be provided separately to individual or some of the gatesand/or bodies of the FETs in the switch arm 350.

In the example configuration 350 of FIG. 14B, N switch circuits havinggate resistance Rg and diode body contact are connected in series toprovide switching functionality between terminals 144, 146. A commonextra resistance R1 is shown to be provided to the gates of the FETs120; and such an extra resistance R1 can be switched ON and OFF by acommon switch S1. In some embodiments, such a switchable extraresistance can be provided separately to individual or some of the gatesand/or bodies of the FETs in the switch arm 350.

The number (N) of switch circuits in the switch arm 350 can be selectedbased on power handling requirement. For example, N can be increased tohandle higher power.

In some embodiments, the extra resistor(s) (R1 and/or R2) and theirrespective switch(es) described in reference to FIGS. 17 and 18 can beimplemented on the same die as the switch circuit(s) 340, off of thedie, or any combination thereof.

In some embodiments, values of the extra resistance(s) (R1 and/or R2)can be selected to optimize or improve IMD performance with minimal orreduced impact on switching time of the switch circuits 340. Such aconfiguration can yield improved IMD performance, including improvementfor low-frequency blockers. For example, the extra resistances (R1 andR2) can be selected to yield high impedances to low-frequency signals atthe gate and body, thereby preventing or reducing such low-frequencysignals from leaking into the gate and body.

In some implementations, and as described herein, the foregoing exampleconfigurations described in reference to FIGS. 17 and 18 can berelatively simpler and easier to implement, and can yield a number ofimprovements. For example, this technique can improve IMD performance ofthe RF switch, including IMD performance at low frequencies.

Summary of Example 3

According to a number of implementations, Example 3 relates to aradio-frequency (RF) switch that includes at least one field-effecttransistor (FET) disposed between first and second nodes, with each ofthe at least one FET having a respective gate and body. The RF switchfurther includes an adjustable-resistance circuit connected to at leastone of the respective gate and body of each FET.

In some embodiments, the FET can be a silicon-on-insulator (SOI) FET. Insome embodiments, the adjustable-resistance circuit can include a firstresistor in series with a parallel combination of a second resistor anda bypass switch. The bypass switch being closed can result in the secondresistor being bypassed to yield a first resistance for theadjustable-resistance, and the bypass switch being open can result in asecond resistance that is greater than the first resistance byapproximately the value of the second resistor. The first resistor caninclude a bias resistor. The second resistance can be selected toimprove intermodulation distortion (IMD) performance, and the firstresistance can be selected to yield a reduced impact on switching timeof the FET.

In some embodiments, the adjustable-resistance circuit can be connectedto the gate. In some embodiments, the RF switch can further include asecond adjustable-resistance circuit connected to the body. In someembodiments, the RF switch can further include a diode body contactconnected to the body.

In some embodiments, the adjustable-resistance circuit can be connectedto the body but not the gate. In some embodiments, the first node can beconfigured to receive an RF signal having a power value and the secondnode is configured to output the RF signal when the FET is in an ONstate. The at least one FET can include N FETs connected in series, withthe quantity N being selected to allow the switch circuit to handle thepower of the RF signal.

In some implementations, Example 3 relates to a method for operating aradio-frequency (RF) switch. The method includes controlling at leastone field-effect transistor (FET) disposed between first and secondnodes so that each FET is in an ON state or an OFF state. The methodfurther includes adjusting a resistance of a circuit connected to atleast one of gate and body of each FET.

In some embodiments, the adjusting can include bypassing one of firstand second resistors that are connected in series.

In accordance with a number of implementations, Example 3 relates to asemiconductor die that includes a semiconductor substrate and at leastone field-effect transistor (FET) formed on the semiconductor substrate.The die further includes an adjustable-resistance circuit connected toat least one of gate and body of each FET.

In some embodiments, the die can further include an insulator layerdisposed between the FET and the semiconductor substrate. The die can bea silicon-on-insulator (SOI) die.

In a number of implementations, Example 3 relates to a method forfabricating a semiconductor die. The method includes providing asemiconductor substrate and forming at least one field-effect transistor(FET) on the semiconductor substrate, with each of the at least one FEThaving a respective gate and body. The method further includes formingan adjustable-resistance circuit on the semiconductor substrate. Themethod further includes connecting the adjustable-resistance circuit toat least one of the gate and the body of each FET.

In some embodiments, the method can further include forming an insulatorlayer between the FET and the semiconductor substrate.

According to some implementations, Example 3 relates to aradio-frequency (RF) switch module that includes a packaging substrateconfigured to receive a plurality of components. The module furtherincludes a semiconductor die mounted on the packaging substrate, withthe die having at least one field-effect transistor (FET). The modulefurther includes an adjustable-resistance circuit connected to at leastone of gate and body of each FET.

In some embodiments, the semiconductor die can be a silicon-on-insulator(SOI) die. In some embodiments, the adjustable-resistance circuit can bepart of the same semiconductor die as the at least one FET. In someembodiments, the adjustable-resistance circuit can be part of a seconddie mounted on the packaging substrate. In some embodiments, theadjustable-resistance circuit can be disposed at a location outside ofthe semiconductor die.

In some implementations, Example 3 relates to a wireless device thatincludes a transceiver configured to process RF signals. The wirelessdevice further includes an antenna in communication with the transceiverconfigured to facilitate transmission of an amplified RF signal. Thewireless device further includes a power amplifier connected to thetransceiver and configured to generate the amplified RF signal. Thewireless device further includes a switch connected to the antenna andthe power amplifier and configured to selectively route the amplified RFsignal to the antenna. The switch includes at least one field-effecttransistor (FET). The switch further includes an adjustable-resistancecircuit connected to at least one of gate and body of each FET.

DESCRIPTION OF EXAMPLE 4

Intermodulation distortion (IMD) measures an unwanted signal added to adesired signal due to mixing products from other RF signals. Such aneffect can be particularly dominant in a multi-mode, multi-bandenvironment. IMD can the result from two or more signals mixing togetherto yield frequencies that are not harmonic frequencies.

System designers typically strive to reduce interference susceptibilitythrough, for example, improved linearity. A given system's linearity cangovern how much IMD will occur within it, which in turn can createinterferences. Through improved linearity of the system building blocks,such as an RF switch, the overall susceptibility of a system tointerference can be decreased.

Performance features such as a lower IMD in RF switches can be animportant factor in wireless-device designs. For example, Long TermEvolution (LTE) systems can benefit significantly from RF switcheshaving reduced IMDs. As a more specific example, system designs forsimultaneous voice and data on LTE (SVLTE) can benefit significantlyfrom RF switches having ultra-low levels of IMDs.

FIG. 15 shows a switching configuration 250 in an example context of asingle-pole-dual-throw (SPDT) application. The single pole is shown tobe connected to an antenna 252. One of the two throws is shown to becoupled to a receive (Rx) port via a switch circuit S. The Rx port canbe coupled to a ground via a shunt switch circuit.

Similarly, the other throw is shown to be coupled to a transmit (Tx)port via a switch circuit S. The Tx port can be coupled to the groundvia a shunt switch circuit.

In some embodiments, each of the switch circuits (“S” and “Shunt”) caninclude one or more FETs such as SOI FETs. A single FET is sometimesreferred to herein with a reference numeral 120 or 122, and a stack ofsuch FETs is sometimes referred to herein with a reference numeral 140or 142. In some embodiments, the “S” and “Shunt” switches can includeone or more features described herein to provide various advantageousfunctionalities.

The switching configuration of FIG. 15 is shown to include capacitors toinhibit a low-frequency blocker from mixing with a fundamentalfrequency. For example, a capacitor Cl is provided between the antennanode and the switch arm S of the Tx throw. Similarly, a capacitor C2 isprovided between the antenna node and the switch arm S of the Rx throw.For the shunt arms, a capacitor C3 is provided between the Tx node andits shunt switch arm. Similarly, a capacitor C4 is provided between theRx node and its shunt switch arm. In some embodiments, a shunt arm mayor may not be provided for the Rx node. With the foregoing capacitors, alow-frequency jammer signal can be blocked or reduced from mixing withany ON or OFF paths. This can lead to improvement in IMD performance,especially for low-frequency blocker signals.

FIG. 16 shows an example operating configuration where some of theforegoing capacitors can provide desirable switching functionalities. Inthe example, the switching configuration is in a transmit mode.Accordingly, the transmit switch arm is ON (closed), and the receiveswitch arm is OFF (open). The shunt arm for the Tx node is OFF (open).

In some embodiments, capacitors C1-C4 described in reference to FIGS. 15and 16 can be implemented on the same die as their respective switchcircuits, off of the die, or any combination thereof.

In some implementations, and as described herein, the foregoing exampleconfigurations described in reference to FIGS. 15 and 16 can berelatively simpler and easier to implement, and can yield a number ofimprovements. For example, this technique can provide improved IMDperformance by preventing a low-frequency blocker signal from mixingwith a fundamental frequency signal.

Summary of Example 4

In some implementations, Example4 relates to a radio-frequency (RF)switch system that includes a switch having a stack of field-effecttransistors (FETs) connected in series between first and second nodes.The system further includes a capacitor connected in series with theswitch and configured to inhibit a low-frequency blocker signal frommixing with a fundamental-frequency signal in the switch.

In some embodiments, the FETs can be silicon-on-insulator (SOI) FETs. Insome embodiments, the first node can be an antenna node. The capacitorcan be disposed between the switch and the antenna node. The switch canbe part of a transmit path such that the second node of the switch is aninput node for an amplified RF signal. The switch can be part of areceive path such that the second node of the switch is an output nodefor an RF signal received from the antenna.

According to some implementations, Example 4 relates to a semiconductordie having a semiconductor substrate and a switch formed on thesemiconductor substrate and having a stack of field-effect transistors(FETs) connected in series. The die further includes a capacitor formedon the semiconductor substrate and connected in series with the switch.The capacitor is configured to inhibit a low-frequency blocker signalfrom mixing with a fundamental-frequency signal in the switch.

In some embodiments, the die can further include an insulator layerdisposed between the FETs and the semiconductor substrate. The die canbe a silicon-on-insulator (SOI) die.

In a number of implementations, Example 4 relates to a method forfabricating a semiconductor die. The method includes providing asemiconductor substrate and forming a stack of field-effect transistors(FETs) on the semiconductor substrate so as to be connected in series.The method further includes forming a capacitor on the semiconductorsubstrate so as to be connected in series with an end of the stack. Thecapacitor is configured to inhibit a low-frequency blocker signal frommixing with a fundamental-frequency signal in the stack.

In some embodiments, the method can further include forming an insulatorlayer between the FETs and the semiconductor substrate.

In accordance with some implementations, Example 4 relates to aradio-frequency (RF) switch module that includes a packaging substrateconfigured to receive a plurality of components. The module furtherincludes a semiconductor die mounted on the packaging substrate. The dieincludes a switch having a stack of field-effect transistors (FETs)connected in series. The module further includes a capacitor connectedin series with the switch. The capacitor is configured to inhibit alow-frequency blocker signal from mixing with a fundamental-frequencysignal in the switch.

In some embodiments, the semiconductor die can be a silicon-on-insulator(SOI) die. In some embodiments, the capacitor can be part of the samesemiconductor die as the FETs. In some embodiments, the capacitor can bepart of a second die mounted on the packaging substrate. In someembodiments, the capacitor circuit can be disposed at a location outsideof the semiconductor die.

In a number of implementations, Example 4 relates to a wireless devicethat includes a transceiver configured to process RF signals. Thewireless device further includes an antenna in communication with thetransceiver. The wireless device further includes a switch moduleinterconnected to the antenna and the transceiver and configured toselectively route RF signals to and from the antenna. The switch moduleincludes a switch having a stack of field-effect transistors (FETs)connected in series. The switch module further includes a capacitorconnected in series with the switch. The capacitor is configured toinhibit a low-frequency blocker signal from mixing with afundamental-frequency signal in the switch.

Examples of Implementations in Products:

Various examples of FET-based switch circuits and bias/couplingconfigurations described herein can be implemented in a number ofdifferent ways and at different product levels. Some of such productimplementations are described by way of examples.

Semiconductor Die Implementation

FIGS. 17A-17D schematically show non-limiting examples of suchimplementations on one or more semiconductor die. FIG. 17A shows that insome embodiments, a switch circuit 120 and a bias/coupling circuit 150having one or more features as described herein can be implemented on adie 800. FIG. 17B shows that in some embodiments, at least some of thebias/coupling circuit 150 can be implemented outside of the die 800 ofFIG. 17A.

FIG. 17C shows that in some embodiments, a switch circuit 120 having oneor more features as described herein can be implemented on a first die800 a, and a bias/coupling circuit 150 having one or more features asdescribed herein can be implemented on a second die 800 b. FIG. 17Dshows that in some embodiments, at least some of the bias/couplingcircuit 150 can be implemented outside of the first die 800 a of FIG.17C.

Packaged Module Implementation

In some embodiments, one or more die having one or more featuresdescribed herein can be implemented in a packaged module. An example ofsuch a module is shown in FIGS. 18A (plan view) and 18B (side view).Although described in the context of both of the switch circuit and thebias/coupling circuit being on the same die (e.g., example configurationof FIG. 18A), it will be understood that packaged modules can be basedon other configurations.

A module 810 is shown to include a packaging substrate 812. Such apackaging substrate can be configured to receive a plurality ofcomponents, and can include, for example, a laminate substrate. Thecomponents mounted on the packaging substrate 812 can include one ormore dies. In the example shown, a die 800 having a switching circuit120 and a bias/coupling circuit 150 is shown to be mounted on thepackaging substrate 812. The die 800 can be electrically connected toother parts of the module (and with each other where more than one dieis utilized) through connections such as connection-wirebonds 816. Suchconnection-wirebonds can be formed between contact pads 818 formed onthe die 800 and contact pads 814 formed on the packaging substrate 812.In some embodiments, one or more surface mounted devices (SMDs) 822 canbe mounted on the packaging substrate 812 to facilitate variousfunctionalities of the module 810.

In some embodiments, the packaging substrate 812 can include electricalconnection paths for interconnecting the various components with eachother and/or with contact pads for external connections. For example, aconnection path 832 is depicted as interconnecting the example SMD 822and the die 800. In another example, a connection path 832 is depictedas interconnecting the SMD 822 with an external-connection contact pad834. In yet another example a connection path 832 is depicted asinterconnecting the die 800 with ground-connection contact pads 836.

In some embodiments, a space above the packaging substrate 812 and thevarious components mounted thereon can be filled with an overmoldstructure 830. Such an overmold structure can provide a number ofdesirable functionalities, including protection for the components andwirebonds from external elements, and easier handling of the packagedmodule 810.

FIG. 19 shows a schematic diagram of an example switching configurationthat can be implemented in the module 810 described in reference toFIGS. 18A and 18B. In the example, the switch circuit 120 is depicted asbeing an SP9T switch, with the pole being connectable to an antenna andthe throws being connectable to various Rx and Tx paths. Such aconfiguration can facilitate, for example, multi-mode multi-bandoperations in wireless devices.

The module 810 can further include an interface for receiving power(e.g., supply voltage VDD) and control signals to facilitate operationof the switch circuit 120 and/or the bias/coupling circuit 150. In someimplementations, supply voltage and control signals can be applied tothe switch circuit 120 via the bias/coupling circuit 150.

Wireless Device Implementation

In some implementations, a device and/or a circuit having one or morefeatures described herein can be included in an RF device such as awireless device. Such a device and/or a circuit can be implementeddirectly in the wireless device, in a modular form as described herein,or in some combination thereof. In some embodiments, such a wirelessdevice can include, for example, a cellular phone, a smart-phone, ahand-held wireless device with or without phone functionality, awireless tablet, etc.

FIG. 20 schematically depicts an example wireless device 900 having oneor more advantageous features described herein. In the context ofvarious switches and various biasing/coupling configurations asdescribed herein, a switch 120 and a bias/coupling circuit 150 can bepart of a module 810. In some embodiments, such a switch module canfacilitate, for example, multi-band multip-mode operation of thewireless device 900.

In the example wireless device 900, a power amplifier (PA) module 916having a plurality of PAs can provide an amplified RF signal to theswitch 120 (via a duplexer 920), and the switch 120 can route theamplified RF signal to an antenna. The PA module 916 can receive anunamplified RF signal from a transceiver 914 that can be configured andoperated in known manners. The transceiver can also be configured toprocess received signals. The transceiver 914 is shown to interact witha baseband sub-system 910 that is configured to provide conversionbetween data and/or voice signals suitable for a user and RF signalssuitable for the transceiver 914. The transceiver 914 is also shown tobe connected to a power management component 906 that is configured tomanage power for the operation of the wireless device 900. Such a powermanagement component can also control operations of the basebandsub-system 910 and the module 810.

The baseband sub-system 910 is shown to be connected to a user interface902 to facilitate various input and output of voice and/or data providedto and received from the user. The baseband sub-system 910 can also beconnected to a memory 904 that is configured to store data and/orinstructions to facilitate the operation of the wireless device, and/orto provide storage of information for the user.

In some embodiments, the duplexer 920 can allow transmit and receiveoperations to be performed simultaneously using a common antenna (e.g.,924). In FIG. 20, received signals are shown to be routed to “Rx” paths(not shown) that can include, for example, a low-noise amplifier (LNA).

A number of other wireless device configurations can utilize one or morefeatures described herein. For example, a wireless device does not needto be a multi-band device. In another example, a wireless device caninclude additional antennas such as diversity antenna, and additionalconnectivity features such as Wi-Fi, Bluetooth, and GPS.

Combination of Features from Different Examples:

In some implementations, various features from different Examplesdescribed herein can be combined to yield one or more desirableconfigurations. FIG. 21 schematically depicts a combinationconfiguration 1000 where a first feature (i,x) is shown to be combinedwith second feature (j,y). The indices “i” and “j” are for Examplenumbers among N Examples, with i=1, 2, . . . , N-1, N, and j=1, 2, . . ., N-1, N. In some implementations, i≠j for the first and second featuresof the combination configuration 1000. The index “x” can represent anindividual feature associated with the i-th Example. The index “x” canalso represent a combination of features associated with the i-thExample. Similarly, the index “y” can represent an individual featureassociated with the j-th Example. The index “y” can also represent acombination of features associated with the j-th Example. As describedherein, the value of N can be 12.

Although described in the context of combining features from twodifferent Examples, it will be understood that features from more thantwo Examples can also be combined. For example, features from three,four, five, etc. Examples can be combined to yield a combinationconfiguration.

General Comments:

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense, as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to.” The word “coupled”, as generally usedherein, refers to two or more elements that may be either directlyconnected, or connected by way of one or more intermediate elements.Additionally, the words “herein,” “above,” “below,” and words of similarimport, when used in this application, shall refer to this applicationas a whole and not to any particular portions of this application. Wherethe context permits, words in the above Detailed Description using thesingular or plural number may also include the plural or singular numberrespectively. The word “or” in reference to a list of two or more items,that word covers all of the following interpretations of the word: anyof the items in the list, all of the items in the list, and anycombination of the items in the list.

The above detailed description of embodiments of the invention is notintended to be exhaustive or to limit the invention to the precise formdisclosed above. While specific embodiments of, and examples for, theinvention are described above for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize. For example, whileprocesses or blocks are presented in a given order, alternativeembodiments may perform routines having steps, or employ systems havingblocks, in a different order, and some processes or blocks may bedeleted, moved, added, subdivided, combined, and/or modified. Each ofthese processes or blocks may be implemented in a variety of differentways. Also, while processes or blocks are at times shown as beingperformed in series, these processes or blocks may instead be performedin parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to othersystems, not necessarily the system described above. The elements andacts of the various embodiments described above can be combined toprovide further embodiments.

While certain embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the disclosure. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the disclosure. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the disclosure.

What is claimed is:
 1. A radio-frequency switch comprising: afield-effect transistor disposed between a first node and a second node,the field-effect transistor having a source, a drain, a gate, and abody; and a coupling circuit including a first path and a second path,the first path being connected between the gate and one of the source orthe drain via a first resistor in series with a first capacitor, thesecond path being connected between the body and the one of the sourceor the drain via a second resistor in series with a second capacitor,the coupling circuit configured to allow discharge of interface chargefrom either or both of the gate and body.